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1 ? fn6020.1 ISL5829 dual 12-bit, +3.3v, 130/210+msps, high speed d/a converter the ISL5829 is a dual 12-bit, 130/210+msps (mega samples per second), cmos, high speed, low power, d/a (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5g or 3g cellular protocols. this device complements the isl5x61 and isl5x29 families of high speed converters, which include 8-, 10-, 12-, and 14- bit devices. pinout ISL5829 (lqfp) top view features ? speed grades . . . . . . . . . . . . . . . . 130m and 210+msps low power . . . . . 233mw with 20ma output at 130msps adjustable full scale output current . . . . . 2ma to 20ma guaranteed gain matching < 0.14db +3.3v power supply 3v lvcmos compatible inputs excellent spurious free dynamic range (73dbc to nyquist, f s = 130msps, f out = 10mhz) umts adjacent channel power = 70db at 19.2mhz edge/gsm sfdr = 90dbc at 11mhz in 20mhz window dual, 3.3v, lower power replacement for ad9765 applications cellular infrastructure - single or multi-carrier: is-136, is-95, gsm, edge, cdm a2000, wcdma, tds-cdma bwa infrastructure quadrature transmit with if range 0?80mhz medical/test instrumentation and equipment wireless communication systems ordering information part number temp. range ( o c) package pkg. no. clock speed ISL5829in -40 to 85 48 ld lqfp q48.7x7a 130mhz ISL5829/2in -40 to 85 48 ld lqfp q48.7x7a 210mhz ISL5829eval1 25 evaluation platform 210mhz 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 qd4 qd5 qd6 qd7 qd8 qd9 qd10 qd11 (msb) clk dgnd agnd qcomp id5 id4 id3 id2 id1 nc sleep d vdd agnd icomp (lsb) id0 nc id6 id7 id8 id9 id10 nc nc qd0 (lsb) qd1 qd2 qd3 id11 (msb) a vdd nc iouta ioutb refio reflo agnd fsadj qoutb qouta nc a vdd data sheet february 2002 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 typical applications circuit +3.3v power source 1 f 50 ? 1.91k ? ferrite 10 h bead r set 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av pp id5 nc id4 id3 id2 nc nc nc qd0 (lsb) qd6 qd7 qd8 qd9 qd10 qd11 (msb) sleep d vdd agnd agnd agnd dgnd qd1 id8 id9 id10 id11 (msb) fsadj refio reflo 0.1 f 0.1 f icomp av pp 0.1 f av pp a vdd a vdd 0.1 f dv pp 0.1 f qcomp clk + 10 f 1 f ferrite 10 h bead dv pp + 10 f 0.1 f 0.1 f 0.1 f c 1 c 2 c 4 c 3 r 1 c 5 c 6 c 9 c 10 l 1 c 12 c 13 c 11 c 14 l 2 (digital power plane) = +3.3v (analog power plane) = +3.3v id6 id7 qd4 qd5 qd2 qd3 id1 (lsb) id0 any 50 ? load represents (50 ? ) (50 ? ) 50 ? 50 ? qout iout 1:1 transformer r 2 r 3 ISL5829
3 functional block diagram upper nc nc (lsb) qd0 qd1 qd2 qd3 qd4 qd7 clk qd5 qd6 5-bit decoder cascode current source switch matrix 38 38 31 msb segments 7 lsbs + qd8 qd9 qd10 (msb) qd11 input latch upper nc nc (lsb) id0 id1 id2 id3 id4 id7 id5 id6 5-bit decoder refio cascode current source switch matrix 38 38 31 msb segments 7 lsbs + id8 id9 id10 (msb) id11 input latch reflo fsadj sleep qouta qoutb iouta ioutb qcomp icomp voltage reference bias generation int/ext ISL5829
4 pin descriptions pin no. pin name pin description 11, 19, 26 agnd analog ground. 13, 24 a vdd analog supply (+2.7v to +3.6v). 28 clk clock input. 27 dgnd connect to digital ground. 10 d vdd digital supply (+2.7v to +3.6v). 20 fsadj full scale current adjust. use a resistor to ground to adjust full scale output current. full scale output current = 32 x v fsadj /r set . 14, 23 nc not internally connected. recommend no connect. 12, 25 icomp, qcomp compensation pin for internal bias gene ration. each pin should be i ndividually decoupled to agnd with a 0.1 f capacitor. 1-6, 29-40, 43-48 id11-id0, qd11-qd0 digital data input ports. bit 11 is most signifi cant bit (msb) and bit 0 is t he least signific ant bit (lsb). 15, 22 iouta, qouta current outputs of the device. full scale output current is achieved when all input bits are set to binary 1. 16, 21 ioutb, qoutb complementary current outputs of the device. full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. 17 refio reference voltage input if internal reference is disabled. the internal reference is not intended to drive an external load. use 0.1 f cap to ground when internal reference is enabled. 18 reflo connect to analog ground to enable internal 1.2v reference or connect to av dd to disable internal reference. 7, 8, 41, 42 nc no connect (nc). not internally connected. no termination required, may be used for device migration to higher resolution dacs. 9 sleep connect to digital ground or leave floating for normal operation. connect to dv dd for sleep mode. ISL5829
5 absolute maximum ratings thermal information digital supply voltage dv dd to dgnd . . . . . . . . . . . . . . . . . . +3.6v analog supply voltage av dd to agnd . . . . . . . . . . . . . . . . . . +3.6v grounds, agnd to dgnd . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v digital input voltages (data, clk, sleep). . . . . . . . . dv dd + 0.3v reference input voltage range . . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c thermal resistance (typical, note 1) ja (c/w) lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25c for all typical values parameter test conditions t a = -40 c to 85 c units min typ max system performance resolution 12 - - bits integral linearity error, inl ?best fit? straight line (note 7) -1.25 0.5 +1.25 lsb differential linearity error, dnl (note 7) -1 0.5 +1 lsb offset error, i os iouta (note 7) -0.006 +0.006 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/c full scale gain error, fse with ex ternal reference (notes 2, 7) -3 0.5 +3 % fsr with internal reference (notes 2, 7) -3 0.5 +3 % fsr full scale gain drift with external reference (note 7) - 50 - ppm fsr/c with internal reference (note 7) - 100 - ppm fsr/c crosstalk f clk = 100msps, f out = 10mhz - 83 - db f clk = 100msps, f out = 40mhz - 74 - db gain matching between channels (dc measurement) as a percentage of full scale range -1.6 0.6 +1.6 % fsr in db full scale range -0.14 0.05 +0.14 db fsr full scale output current, i fs 22022 ma output voltage compliance range (note 3) -1.0 - 1.25 v dynamic characteristics maximum clock rate, f clk ISL5829/2in 210 250 - mhz maximum clock rate, f clk ISL5829in 130 150 - mhz output rise time full scale step - 1 - ns output fall time full scale step - 1 - ns output capacitance -5 - pf output noise ioutfs = 20ma - 50 - pa/ hz ioutfs = 2ma - 30 - pa/ hz ISL5829
6 ac characteristics (using figure 13 with r diff = 50 ? and r load = 50 ? , full scale output = -2.5dbm ) spurious free dynamic range, sfdr within a window f clk = 210msps, f out = 80.8mhz, 30mhz span (notes 4, 7) - 72 - dbc f clk = 210msps, f out = 40.4mhz, 30mhz span (notes 4, 7) - 78 - dbc f clk = 130msps, f out = 20.2mhz, 20mhz span (notes 4, 7) - 84 - dbc spurious free dynamic range, sfdr to nyquist (f clk /2) f clk = 210msps, f out = 80.8mhz (notes 4, 7) - 54 - dbc f clk = 210msps, f out = 40.4mhz (notes 4, 7, 9) - 65 - dbc f clk = 200msps, f out = 20.2mhz, t = 25c (notes 4, 7) 60 66 - dbc f clk = 200msps, f out = 20.2mhz, t = -40c to 85c (notes 4, 7) 58 - - dbc f clk = 130msps, f out = 50.5mhz (notes 4, 7) - 57 - dbc f clk = 130msps, f out = 40.4mhz (notes 4, 7) - 62 - dbc f clk = 130msps, f out = 20.2mhz (notes 4, 7) - 69 - dbc f clk = 130msps, f out = 10.1mhz, t = -40 o c to 85 o c (notes 4, 7) 68 73 - dbc f clk = 130msps, f out = 5.05mhz (notes 4, 7) - 77 - dbc f clk = 100msps, f out = 40.4mhz (notes 4, 7) - 60 - dbc f clk = 80msps, f out = 30.3mhz (notes 4, 7) - 63 - dbc f clk = 80msps, f out = 20.2mhz (notes 4, 7) - 70 - dbc f clk = 80msps, f out = 10.1mhz (notes 4, 7, 9) - 73 - dbc f clk = 80msps, f out = 5.05mhz (notes 4, 7) - 76 - dbc f clk = 50msps, f out = 20.2mhz (notes 4, 7) - 66 - dbc f clk = 50msps, f out = 10.1mhz (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 5.05mhz (notes 4, 7) - 77 - dbc spurious free dynamic range, sfdr in a window with eight tones f clk = 210msps, f out = 28.3mhz to 45.2mhz, 2.1mhz spacing, 50mhz span (notes 4, 7, 9) -64 - dbc f clk = 130msps, f out = 17.5mhz to 27.9mhz, 1.3mhz spacing, 35mhz span (notes 4, 7) -67 - dbc f clk = 80msps, f out = 10.8mhz to 17.2mhz, 811khz spacing, 15mhz span (notes 4, 7) -74 - dbc f clk = 50msps, f out = 6.7mhz to 10.8mhz, 490khz spacing, 10mhz span (notes 4, 7) -75 - dbc spurious free dynamic range, sfdr in a window with edge or gsm f clk = 78msps, f out = 11mhz, in a 20mhz window, rbw = 30khz (notes 4, 7, 9) -90 - dbc adjacent channel power ratio, acpr with umts f clk = 76.8msps, f out = 19.2mhz, rbw = 30khz (notes 4, 7, 9) - 70 - db voltage reference internal reference voltage, v fsadj pin 20 voltage with internal reference 1.2 1.23 1.3 v internal reference voltage drift - 40 - ppm/c internal reference output current sink/source capability reference is not intended to drive an external load - 0 - a reference input impedance -1 -m ? reference input multiplying bandwidth (note 7) - 1.0 - mhz digital inputs d11-d0, clk input logic high voltage with 3.3v supply, v ih (note 3) 2.3 3.3 - v electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25c for all typical values (continued) parameter test conditions t a = -40 c to 85 c units min typ max ISL5829
7 input logic low voltage with 3.3v supply, v il (note 3) - 0 1.0 v sleep input current, i ih -25 - +25 a input logic current, i ih, il -20 - +20 a clock input current, i ih, il -10 - +10 a digital input capacitance, c in -3 - pf timing characteristics data setup time, t su see figure 15 - 1.5 - ns data hold time, t hld see figure 15 - 1.5 - ns propagation delay time, t pd see figure 15 - 1 - clock period clk pulse width, t pw1 , t pw2 see figure 15 (note 3) 2 - - ns power supply characteristics av dd power supply (note 8) 2.7 3.3 3.6 v dv dd power supply (note 8) 2.7 3.3 3.6 v analog supply current (i avdd ) 3.3v, ioutfs = 20ma - 60 62 ma 3.3v, ioutfs = 2ma - 24 - ma digital supply current (i dvdd ) 3.3v (note 5) - 11 15 ma 3.3v (note 6) - 17 21 ma supply current (i avdd ) sleep mode 3.3v, ioutfs = don?t care - 5 - ma power dissipation 3.3v, ioutfs = 20ma (note 5) - 233 255 mw 3.3v, ioutfs = 20ma (note 6) - 253 274 mw 3.3v, ioutfs = 2ma (note 5) - 115 - mw power supply rejection single supply (note 7) -0.125 - +0.125 %fsr/v notes: 2. gain error measured as the error in the ratio betw een the full scale output current and the current through r set (typically 625 a). ideally the ratio should be 32. 3. parameter guaranteed by design or char acterization and not production tested. 4. spectral measurements made with different ial transformer coupled output and no external filtering. for multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 5. measured with the clock at 130m sps and the output frequency at 10mhz. 6. measured with the clock at 200m sps and the output frequency at 20mhz. 7. see definition of specifications . 8. recommended operation is from 3.0v to 3.6v. operation below 3.0v is possi ble with some degradation in spectral performance. r eduction in analog output current may be necessary to maintain spectral performance. 9. see typical performance plots. electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25c for all typical values (continued) parameter test conditions t a = -40 c to 85 c units min typ max ISL5829
8 typical performance (+3.3v supply, using figure 13 with r diff = 100 ? and r load = 50 ? ) figure 1. edge at 11mhz, 78msps clock (91+dbc @ ? f = +6mhz) figure 2. edge at 11mhz, 78msps clock (75dbc -nyquist, 6db pad) figure 3. gsm at 11mhz, 78msps clock (90+dbc @ ? f = +6mhz, 3db pad) figure 4. gsm at 11mhz, 78msps clock (75dbc - nyquist, 9db pad) figure 5. four edge carriers at 12.4?15.6mhz, 800khz spacing, 78msps (71dbc - 20mhz window) figure 6. four gsm carriers at 12.4?15.6mhz, 78msps (73dbc - 20mhz window, 6db pad) spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw ISL5829
9 figure 7. umts at 19.2mhz, 76.8msps (70db 1stacpr, 70db 2ndacpr) figure 8. one tone at 10.1mhz, 80msps clock (71dbc - nyquist, 6db pad) figure 9. one tone at 40.4mhz, 210msps clock (61dbc - nyquist, 6db pad) figure 10. eight tones (crest factor=8.9) at 37mhz, 210msps clock, 2.1mhz spacing (65dbc - nyquist) figure 11. two tones (ckhzf=6) at 8.5mhz, 50msps clock, 500khz spacing (82dbc - 10mhz window, 6db pad) figure 12. four tones (cf=8.1) at 14mhz, 80msps clock, 800khz spacing (70dbc - nyquist, 6db pad) typical performance (+3.3v supply, using figure 13 with r diff = 100 ? and r load = 50 ? ) (continued) spectral mask umts tdd p>43dbm bts ISL5829
10 definition of specifications adjacent channel power ratio, acpr, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. crosstalk, is the measure of the channel isolation from one dac to the other. it is measured by generating a sinewave in one dac while the other dac is clocked with a static input, and comparing the output power of each dac at the frequency generated. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be one lsb. a dnl specification of one lsb or less guarantees monotonicity. edge, enhanced data for global evolution, a tdma standard for cellular applications which uses 200khz bw, 8-psk modulated carriers. full scale gain drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per c. full scale gain error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through r set ). gain matching, is a measure of the full scale amplitude match between the i and q channels given the same input pattern. it is typically measured with all 1s at the input to both channels, and the full sca le output voltage developed into matching loads is compared for the i and q outputs. gsm, global system for mobile communication, a tdma standard for cellular applications which uses 200khz bw, gmsk modulated carriers. integral linearity error, inl, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. internal reference voltage drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm per c. offset drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage at iouta through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per degree c. offset error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of iouta through a known resistance. offset error is defined as the maximum deviation of the iouta output current from a value of 0ma. output voltage compliance range, is the voltage limit imposed on the output. the output impedance should be chosen such that the voltage developed does not violate the compliance range. power supply rejection, is measured using a single power supply. the nominal supply voltage is varied 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage re ference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the frequency is increased until the amplitude of the output waveform is 0.707 (-3db) of its original value. spurious free dynamic range, sfdr , is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. total harmonic distortion, thd, is the ratio of the rms value of the fundamental out put signal to the rms sum of the first five harmonic components. umts, universal mobile telecommunications system, a w-cdma standard for cellular applications which uses 3.84mhz modulated carriers. detailed description the ISL5829 is a dual 12-bit, current out, cmos, digital to analog converter. the core of each dac is based on the isl5861. the maximum update ra te is at least 210+msps and can be powered by a single power supply in the recommended range of +3.0v to +3.6v. operation with clock rates higher than 210msps is possible; please contact the factory for more information. it consumes less than 125mw of power per channel when using a +3.3v supply, the maximum 20ma of output current, and the data switching at 210msps. the architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. in previous architectures that containe d all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially lar ger amount of current turning on and off at certain, worst-ca se transition points such as midscale and quarter scale transitions. by greatly reducing the amount of current switching at these major transitions, the overall glitch of the conver ter is dramatically reduced, improving settling time, transient problems, and accuracy. digital inputs and termination the ISL5829 digital inputs are formatted as offset binary and guaranteed to 3v lvcmos levels. the internal register is updated on the rising edge of the clock. to minimize ISL5829
11 reflections, proper terminatio n should be implemented. if the lines driving the clock and the digital inputs are long 50 ? lines, then 50 ? termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). these termination resistors are not likely needed as long as the digital waveform source is within a few inches of the dac. for pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50- 200 ?) prior to the dac?s inputs in order to reduce the amount of noise. power supply separate digital and analog power supplies are recommended. the allowable supply range is +2.7v to +3.6v. the recommended supply range is +3.0 to 3.6v (nominally +3.3v) to maintain optimum sfdr. however, operation down to +2.7v is possible with some degradation in sfdr. reducing the analog output current can help the sfdr at +2.7v. the sfdr values stated in the table of specifications were obtained with a +3.3v supply. ground planes separate digital and analog ground planes should be used. all of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. the same is true for the analog components and the analog ground plane. noise reduction to minimize power supply noise, 0.1 f capacitors should be placed as close as possible to the converter?s power supply pins, av dd and dv dd . also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. voltag e reference the internal voltage reference of the device has a nominal value of +1.23v with a 40ppm/c drift coefficient over the full temperature range of the converter. it is recommended that a 0.1 f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin selects the reference. the internal reference can be selected if reflo is tied low (ground). if an external reference is desired, then reflo should be tied high (the analog supply voltage) and the external reference driven into refio. the full scale output current of the converter is a function of the voltage reference used and the value of r set . i out should be within the 2ma to 22ma range, though operation below 2ma is possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.2v. if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set) x 32. if the full scale output current is set to 20ma by using the internal voltage reference (1.23v) and a 1.91k ? r set resistor, then the input coding to output current will resemble the following: analog output iouta and ioutb are complementary current outputs. the sum of the two currents is always equal to the full scale output current minus one lsb. if single ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unused output be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -1.0v to 1.25v. r out (the impedance loading each current output) should be chosen so that the desired output voltage is produ ced in conjunction with the output full scale current. if a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. the output voltage equation is: v out = i out x r out . the most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. the maximum recommended output current is 20ma. differential output iouta and ioutb can be used in a differential-to-single- ended arrangement to achieve better harmonic rejection. with r diff = 50 ? and r load =50 ? , the circuit in figure 13 will provide a 500mv (-2.5dbm) signal at the output of the transformer if the full scale output current of the dac is set to 20ma (used for the electrical s pecifications table). values of r diff = 100 ? and r load =50 ? were used for the typical performance curves to increase the output power and the dynamic range. the center tap in figure 13 must be grounded. in the circuit in figure 14, the user is left with the option to ground or float the center tap. the dc voltage that will exist at either iouta or ioutb if the center tap is floating is iout dc x (r a //r b ) v because r diff is dc shorted by the transformer. if the center tap is grounded, the dc voltage is 0v. recommended values for the circuit in figure 14 are table 1. input coding vs output current with internal reference (1.23v typ) and rset=1.91k ? input code (d11-d0) iouta (ma) ioutb (ma) 1111 1111 1111 20.6 0 1000 0000 0000 10.3 10.3 0000 0000 0000 0 20.6 ISL5829
12 r a =r b =50 ? , r diff =100 ? , assuming r load =50 ? . the performance of figure 13 and figure 14 is basically the same, however leaving the center tap of figure 14 floating allows the circuit to find a more balanced virtual ground, theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations. propagation delay the converter requires two clock rising edges for data to be represented at the output. ea ch rising edge of the clock captures the present data wo rd and outputs the previous data. the propagation delay is t herefore 1/clk, plus <2ns of processing. see figure 15. test service intersil offers customer-specific testing of converters with a service called testdrive. to submit a request, fill out the testdrive form at www.intersil.com/testdrive. or, send a request to the technical support center. r diff ISL5829 r load figure 13. output loading for datasheet measurements outa outb v out = (2 x outa x r eq )v l oad seen by the transformer r load represents the 1:1 r eq = 0.5 x (r load // r diff ) at each output figure 14. alternative output loading ISL5829 outa outb v out = (2 x outa x r eq )v r eq = 0.5 x (r load // r diff // r a ), where r a =r b at each output r load r diff r a r b load seen by the transformer r load represents the timing diagram figure 15. propagation delay, setup time, hold time and minimum pulse width diagram clk i out 50% t pw1 t pw2 t su t hld t su t su t pd t hld t hld d11-d0 w 0 w 1 w 2 w 3 output=w 0 output=w 1 t pd output=w -1 ISL5829
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL5829 thin plastic quad flat pack packages (lqfp) d d1 e e1 -a- pin 1 a2 a1 a 11 o -13 o 11 o -13 o 0 o -7 o 0.020 0.008 min l 0 o min plane b 0.004/0.008 0.09/0.20 with plating base metal seating 0.004/0.006 0.09/0.16 b1 -b- e 0.003 0.08 a-b s d s c m 0.08 0.003 -c- -d- -h- 0.25 0.010 gage plane q48.7x7a (jedec ms-026bbc issue b) 48 lead thin plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.062 - 1.60 - a1 0.002 0.005 0.05 0.15 - a2 0.054 0.057 1.35 1.45 - b 0.007 0.010 0.17 0.27 6 b1 0.007 0.009 0.17 0.23 - d 0.350 0.358 8.90 9.10 3 d1 0.272 0.280 6.90 7.10 4, 5 e 0.350 0.358 8.90 9.10 3 e1 0.272 0.280 6.90 7.10 4, 5 l 0.018 0.029 0.45 0.75 - n48 487 e 0.020 bsc 0.50 bsc - rev. 2 1/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. ?n? is the number of terminal positions. -c- -h-

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